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DO-254: Boost verification coverage by test

Posted: 21 Jan 2013     Print Version  Bookmark and Share

Keywords:DO-254  aviation  Hardware Description Language 

5. Use the test vectors for MIN/TYP/MAX post-layout timing simulation of the design.

6. Test the target device in isolation, at-speed, with the test vectors as test inputs. Ensure that the hardware testing setup provides 100 per cent input controllability and output access points, so that the same test cases used for simulation are used for hardware test. Further efficiencies can be achieved if device testers used are able to generate results viewable in simulator waveform viewer. This way, simulation waveforms can be compared easily with device testing waveforms.

7. After testing the target device in isolation, proceed to final board testing with the flight configuration of the board to verify board level functions, components interfaces and environmental requirements.

Figure 3: Increasing verification coverage by test.

Device testing with DO-254/CTS
Aldec's DO-254/CTS can be employed to facilitate the recommendations described in this paper. DO-254/CTS consists of custom hardware and software that provide at-speed testing for the target device with the testbench applied as test inputs. Utilising the testbench as test inputs during device testing ensures that all requirements verified in simulation are also verified by test. The product is custom and specific to the design under test and target device. The target FPGA device under test is isolated in a daughter board such that a functional test with 100 per cent input control and output access points are feasible.

Figure 4: DO-254/CTS Methodology.

Robustness testing is simplified with DO-254/CTS especially for test cases describing input and clock frequency variations. For the inputs, test cases for interrupted, invalid and unexpected inputs and out of range data bus can easily be implemented in the testbench, hence they can also be implemented and applied to the device during testing because DO-254/CTS utilises the test vectors generated from simulation. For the clocks, DO-254/CTS provides complete controllability of the oscillators that are used for applying the test vectors, clocking the DUT and capturing the results. The clocks settings and variations are configurable and fully scriptable. The phase of clocks can be shifted with a step of 1/256 of clock's frequency while the input data remains constant. For example, if clock is running at 128MHz, the clock edge position can be shifted against the data with about 30ps step.

The key features of DO-254/CTS are the following:

 • At-speed verification in the target device (Altera, Lattice, Microsemi and Xilinx)
 • Reuse testbench as test inputs for device testing
 • Leverage test cases from simulation
 • Increase verification coverage by test
 • Enables requirements-based testing
 • Robustness testing is simplified (fully scriptable)
 • No changes in the design and testbench
 • FPGA design and verification can be performed immediately without the final board
 • Results visualisation with simulator waveform viewer

While the guidance is vague as to how much verification should be achieved via simulation or test, it is quite clear that requirements describing device pin level behaviour must be verified by test in order to satisfy requirements. Verification coverage by test during final board testing is difficult and in most cases not feasible. Frequently as a result, applicants are left with the only option to verify them only by simulation. But simulation is insufficient and in many cases unable to expose errors that may impact safety and reliability of the device under test. As a solution and as the main part of the recommendations provided in this paper, Aldec's DO-254/CTS augments board level testing to increase verification coverage by test. DO-254/CTS provides 100-per cent verification coverage by test with 100-per cent FPGA input control necessary to implement requirements-based and robustness test cases. DO-254/CTS leverages the same test cases and test stimulus implemented in simulation for device testing which offers a more efficient verification approach and the ability to cut the verification cycle.

[1] FAA Advisory Circular 20-152, "Subject: RTCA, INC., Document RTCA/DO-254, Design Assurance Guidance for Airborne Electronic Hardware", 2005, pg1,
[2][3][4] RTCA/DO-254 "Design Assurance Guidance for Airborne Electronic Hardware", 2000, pg 1, pg 39, pg 41,
[5][6][7] EASA Certification Memo SWCEH – 001, "Subject Development Assurance of Airborne Electronic Hardware", 2012, pg 36, pg 37, pg 38,
[8] FAA Order 8110-105, "Subject: Simple and Complex Electronic Hardware Approval Guidance", 2008, pg 31,
[9] Louie De Luna, Zibi Zalewski "FPGA Level In-Hardware Verification for DO-254 Compliance", IEEE, Digital Avionics Systems Conference (DASC) 2011, pg2

About the authors
Louie De Luna is DO-254 Program Manager from Aldec Inc.

Randall Fulton a Federal Aviation Administration Consultant DER.

To download the PDF version of this article, click here.

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