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Design video systems with all programmable SoC

Posted: 23 Jan 2013     Print Version  Bookmark and Share

Keywords:SoC  processing system  video systems  programmable logic 

With processing systems such as the Xilinx Zynq-7000 All Programmable SoC, customers want to fully utilise the processing system (PS) and custom peripherals connected to the PS within the device. An example of this is multiple video pipelines in which live video streams are written into memory (input) and memory is read to send out live video streams (output) in which the processor is accessing memory. This application note covers design principles that target customers needing high performance from the Zynq-7000 AP SoC memory interfaces, from AXI master interfaces implemented in the programmable logic (PL), and from the ARM Cortex-A9 processor(s).

With video systems, guaranteed worst-case latency is required for the video streams to ensure that frames are not dropped or corrupted. To provide high-speed AXI master interfaces in the PL with lower latency and direct access to the Zynq-7000 AP SoC memory interfaces, connections to the high performance (HP) interfaces are required. The Zynq-7000 AP SoC contains four HP interfaces that are 64bit or 32bit AXI3 slave interfaces designed for high throughput.

View the PDF document for more information.

Originally published by Xilinx Inc. at as "Designing High-Performance Video Systems with the Zynq-7000 All Programmable SoC".

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