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Assess power savings from intelligent clock gating

Posted: 18 Jan 2013     Print Version  Bookmark and Share

Keywords:FPGA  Intelligent clock gating  design tools 

This application note introduces FPGA designers to intelligent clock gating by describing clock gating support in the Xilinx design tools while supplying a detailed analysis of the impact of clock gating on a design from a logic design and power perspective. Accessing and invoking clock gating support in the Xilinx design tools flow and how to analyse the results is also outlined.

Intelligent clock gating is a set of algorithms that can detect unnecessary switching in the design and suppress it. This fully automated method adds a small amount of logic to suppress and minimise nonessential activity in the design, which reduces the power consumed by the design.

View the PDF document for more information.

Originally published by Xilinx Inc. at as "Analysis of Power Savings from Intelligent Clock Gating"

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