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Using Vivado HLS for floating-point design

Posted: 10 Jan 2013     Print Version  Bookmark and Share

Keywords:Register Transfer Level  RTL 

This application note discusses how the Vivado High-Level Synthesis (HLS) tool transforms a C/C++ design specification into a Register Transfer Level (RTL) implementation for designs that need floating-point calculations. While the basics of performing HLS on floating-point designs are reasonably straightforward, there are some more subtle aspects that merit detailed explanation. This application note presents details on the basics and advanced topics relating to design performance, area, and verification of implementing floating-point logic in Xilinx FPGAs using the Vivado HLS tool.

View the PDF document for more information.

Originally published by Xilinx Inc. at as "Floating-Point Design with Vivado HLS".

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