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Altera backs FDSOI process for FPGAs

Posted: 20 Dec 2012     Print Version  Bookmark and Share

Keywords:FPGA  FDSOI 

Altera's evaluation of fully-depleted silicon on insulator (FDSOI) chip manufacturing process concludes that the technology could have particular benefits for FPGAs.

This raises the possibility that Altera could be considering replacing Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan) as its foundry of choice or operating a multiple-foundry manufacturing strategy in the future.

Jeff Watt, an Altera fellow and technology development specialist, presented An evaluation and benchmarking of 14nm fully-depleted technology for FPGAs at an evening symposium on FDSOI held alongside the International Electron Devices Meeting in San Francisco.

Altera is reported to be engaged with TSMC for the 20nm bulk planar CMOS node due to ramp in 2013 but concerns have been raised that the node will be power hungry. Grenoble research institute Leti, SOI wafer maker Soitec and IBM have been partners with STMicroelectronics NV (Geneva, Switzerland) in the development of the FDSOI process, and ST has added a licensing deal with Globalfoundries Inc. (Milpitas, Calif.) that could increase manufacturing capacity. TSMC is not known to be working on FDSOI but has indicated it plans a rapid transition to a 16nm FinFET manufacturing process as its next-generation technology in 2014.

In his presentation Watt concluded that planar FDSOI has advantages for ICs in general but has particular benefits for FPGA circuits. His presentation made comparisons between bulk planar CMOS at 28nm and FDSOI planar CMOS at 14nm suggesting that Watt has adopted the convention that the next FDSOI node after 28nm should be labelled 14nm FDSOI.

Watt said in his presentation that 14nm FDSOI could give a 35 per cent performance improvement compared with 28nm bulk planar CMOS at the same switching power or a 32 per cent lower switching power at the same delay time. Watt also showed how the use of body bias to effect power/delay trade-off customisation over a wide range could be attractive to the FPGA maker.

Altera's interest could be a possible fall out of supply problems experienced by customers of 28nm bulk CMOS manufacturing at TSMC during 2012. There was speculation at that time that Altera might turn to Intel as a foundry supplier that could offer leading-edge FinFET manufacturing process technology. If Altera opts to build some FPGAs on FDSOI it would likely be supplied by Globalfoundries as ST only has pilot line capability at its wafer fab in Crolles.

TSMC has reportedly secured large orders for FPGAs to be made using next-generation 20nm bulk planar CMOS from both Altera and its rival Xilinx. Altera was rumoured to be the first company to commit to TSMC's 20nm planar bulk CMOS process, which is expected to ramp in 2013. In addition both Altera and Xilinx are thought to be interested in multi-chip packaging using TSMC's CoWoS (chip on wafer on substrate) process but TSMC has yet to begin volume production of 20nm.

However, a dual-foundry or multiple foundry manufacturing strategy could create difficulties for Altera. One of the benefits of staying loyal to one foundry is early access to process technology, something that is vital to FPGA vendors. There could be concerns that TSMC would provide better support and access to the customer that is 100 per cent loyal.

- Peter Clarke
  EE Times

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