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Power tip: Designing power supply control loop

Posted: 05 Dec 2012     Print Version  Bookmark and Share

Keywords:simulator  power supply  control loops 

P-SPICE (or any simulator) can be quite effective in synthesising power supply control loops. In this power tip, we employ P-SPICE to design a control loop for the integrated, synchronous buck shown in figure 1.

This IC uses a transconductance error amplifier and internal voltage reference. The output voltage is sampled through R6 and R7 and is compared to an internal reference of 0.8V. The error amplifier generates a current out of the COMP pin (8) that is proportional to the difference. The current then flows through the compensation impedances to ground and generates a voltage which controls inductor L1 current to maintain output voltage regulation. The IC uses current mode control (CMC) to effectively turn the output inductor L1 into a current source. The current in L1 varies proportionally to the error amplifier voltage on the COMP pin. The inductor current then flows through the output capacitor and load resistance to generate a voltage which closes the loop.

Figure 1: This current mode, integrated switcher uses type 3 compensation to boost bandwidth.

Figure 2 shows a P-SPICE model based on the schematic in figure 1. The compensation components (R3, C3, and C13) and voltage divider resistors are unchanged from the schematic.

Differences between the schematic and the model include:

1) modelling the transconductance amplifier and power stage as voltage-controlled current sources

2) adding reramp and capacitance to C7 to model the internal parasitic elements associated with the error amp

3) modifying the C11 output capacitance from 47 uF to 30 uF to account for its capacitance reduction as a function of DC bias voltage

4) adding VAC so loop gain can be measured as a ratio of the injected voltage to the return voltage

5) adding delay line T1 and terminating impedance Rdl. This last change is used to model the sampling delay of the control circuit.

There is a finite time from when the circuit should switch states until it actually does. This average delay time is half the switching period, so a delay line of that time is added. A 50 ohm resistor is used to properly terminate the line.

Figure 2: A delay line in this P-Spice model simulates sampling delay.

Figure 3 is the measured power supply loop gain shown in figure 1. The power supply operating frequency is 600kHz and the cross-over frequency approaches 200kHz, or one-third the switching frequency. At this high ratio of cross-over to switching frequency, the modulator's phase lag becomes significant. At 300kHz (half the switching frequency), the sampling delay introduces 90 degrees of phase lag.

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