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Why JESD204B suits wideband data converter apps

Posted: 21 Nov 2012     Print Version  Bookmark and Share

Keywords:JESD204A  JESD204B  serial LVDS 

In 2006 JEDEC published the JESD204 specification for a single 3.125-Gbps data lane. The JESD204 interface is self-synchronous, so there is no need to calibrate the length of the PCB wire traces to avoid clock skew. JESD204 leverages the SerDes ports offered on many FPGAs to free up general-purpose I/O.

JESD204A, published in 2008, adds support for multiple time-aligned data lanes and lane synchronisation. This enhancement makes it possible to use higher bandwidth data converters and multiple synchronised data converter channels and is particularly important for wireless infrastructure transceivers used in cellular base stations. JESD204A also provides multi-device synchronisation support which is useful for devices, such as medical imaging systems, that use large numbers of ADCs.

JESD204B, the third revision of the spec, increases the maximum lane rate to 12.5Gbit/s. JESD204B also adds deterministic latency, which communicates synchronisation status between the receiver and transmitter. Harmonic clocking, also introduced in JESD204B, makes it possible to derive a high-speed data converter clock from a lower-speed input clock with deterministic phasing.

Figure 3: JESD204 with its high speed serial I/O capability solves the system PCB complexity challenge.

Summary
The JESD204B industry serial interface standard reduces the number of digital inputs and outputs between high-speed data converters and FPGAs and other devices. Fewer interconnects simplifies layout and makes it possible to achieve a smaller form factor (figure 3). These advantages are important for a wide range of high-speed data converter applications such as wireless infrastructure transceivers, software defined radios, medical imaging systems, and radar and secure communications.

About the author
George Diniz is a Product Line Manager in High Speed Digital to Analog Converters at Analog Devices in Greensboro, NC. He leads a team responsible for the development of JESD204B Rx and Tx interface cores, which are integrated into High Speed Analog to Digital and Digital to Analog converter products.

George has 25 years of experience in the semiconductor industry and has held various roles in design engineering and product line management. Before joining Analog Devices, George was a design engineer at IBM, where he was engaged in mixed-signal design of custom SRAM macros, PLL and DLL functions for PowerPC processors. He has an MSEE from North Carolina State University and a BEE from Manhattan College. For recreation, George enjoys outdoor activities, restoring automobiles and running.

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