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Grey Cell method for RTL analysis of FPGA designs

Posted: 19 Nov 2012     Print Version  Bookmark and Share

Keywords:RTL analysis  clock domain crossing  Verification 

As designs become more complex, we are seeing two major issues that customers have to deal with in the RTL analysis space.

The first issue has to do with sheer design size and the associated data volume. As designs go through several iterations before they stabilise, it is inefficient to be dragging along every piece of design information all the time. It thus becomes incumbent upon EDA providers to alleviate the pain with new methodologies which can efficiently handle the data volume.

The second issue has to do with the increased use of purchased semiconductor Intellectual Property (IP) blocks. On average, every design brings together 50 to 100 different IPs that need to work well together. In most cases, designers who are using the IPs either do not know the inside of the IP well or do not have the information, which then adds tremendous difficulty during integration and verification because inter-IP issues are becoming predominant. It befits EDA providers to make inter-block RTL analysis possible.

By analogy, the first issue can be compared to the need for a hierarchical approach and the second issue to the increased importance of parasitic extraction as most delays reside outside the gates. In this article, we will show how Blue Pearl enables a methodology that relieves both issues with the Grey Cell methodology.

What is a Grey Cell?
A Grey Cell, as depicted in figure 1, is a representation of a module that excludes all register-to-register logic. It contains only the logic from each input up to and including the nearest register, and all logic from each output back to and including the nearest register. A grey cell differs from a black box in that a black box has no logic inside. Grey cells enable the analysis of module-to-module connections while making abstraction of the details and/or preserving the trade secrets of the original IP provider.

Figure 1: Grey cell vs. black box.

When a module is declared as a Grey Cell, Blue Pearl will disable some checks e.g. dangling nets, since the module does not contain the complete RTL representation. In general, IP providers will specify to their customers when they are providing a Grey Cell model. However, in case a designer sees superfluous messages for a purchased IP, the designer should confirm with the IP provider if indeed a Grey Cell model.

It is straightforward to define a module as a Grey Cell using the Blue Pearl Software Suite. The designer has to select the module and then declare it as a Grey Cell in the Module Options menu, as shown in figure 2.

Figure 2: How to define a Grey Cell.

Handling massive designs
To illustrate the leading issue described in the first section of this article, let's assume that all the cells shown in figure 3 are part of the same module. In this portion of the design, the Blue Pearl Software Suite has detected a clock domain crossing (CDC) starting at the flip-flop labelled "previous_complete" and ending at the flip-flop labelled "repeated_access_ack". Notice that the path is completely contained within the module. The designer would thus take the necessary action to fix any CDC issues within the module.

Figure 3: CDC detected during RTL analysis.


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