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EE Times-India > EDA/IP

Open-Silicon taps Synosys Galaxy platform for high-performance design

Posted: 04 Oct 2012     Print Version  Bookmark and Share

Keywords:place and route  quad-core  ARM  Cortex-A9 

Open-Silicon used Synopsys Inc.'s IC Compiler place and route solution to achieve 1.3GHz performance on a quad-core ARM Cortex-A9 MPCore processor.

IC Compiler is a cornerstone of the Synopsys Galaxy Implementation Platform, and its advanced optimisation technologies, unique leakage power recovery capability and predictable flow with Synopsys Design Compiler Graphical synthesis solution were key contributors to Open-Silicon achieving the performance and power targets and predictable timing closure for the hardened processor core, according to the companies.

"We established the Centre of Excellence for ARM based designs to provide our customers with complete ARM solutions from ARM sub-system design to power and performance-optimised processor hard macros," said Taher Madraswala, senior vice president of Engineering, Open-Silicon. "For performance optimisation, we collaborated with Synopsys to leverage innovative technologies from the Galaxy Platform to enable the 1.3GHz frequency that our customers need to differentiate themselves in the market."

The quad-core processor targeted at a set-top box application was a sizeable design totalling more than three million instances with hundreds of macros, including four ARM NEON media processing engines. Implemented hierarchically, the design achieved a frequency of 1.3GHz at the typical corner using 69 per cent low-power long channel cells. Open-Silicon optimised the hard macro for a TSMC 40LP low-power process using ARM POP IP, comprised of standard cells and memories, as well as Synopsys' high-speed DesignWare Embedded Memories.

According to the companies, the factors that made timing closure a challenging task included:

� Additional levels of logic were introduced by the complexity of the quad-core configuration.

� The high cell density required for a compact core amplified timing sensitivity to placement, requiring tighter correlation between synthesis and place and route.

� Top-level floor planning required careful tuning to improve timing and area.

� Performance was the highest priority, but leakage power also had to be managed.

� The parts of the design related to memory access run at twice the processor clock speed (half clock cycle), further straining timing closure.

The Open-Silicon design team created a flow with Design Compiler Graphical and IC Compiler that converged on timing quickly and predictably. They took full advantage of key capabilities such as:

� Design Compiler Graphical's physical guidance for 20 per cent improved timing and 5 per cent post-route correlation with IC Compiler.

� IC Compiler's useful skew technology to close timing on the memory half cycle paths.

� IC Compiler's final-stage leakage recovery that delivered a 5X reduction in the number of high power cells without impacting performance.

Other Galaxy platform tools used in the quad-core implementation include Formality for equivalence checking as well as StarRC and PrimeTime for signoff extraction and timing analysis.

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