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How to interface QDR-II+ synchronous SRAM with high-speed FPGAs (Part 2)

Posted: 01 Oct 2012     Print Version  Bookmark and Share

Keywords:QDRII  FPGA  IP blocks 

Part 1 of this series focuses on the hardware aspects required for interfacing QDRII+ memory with an FPGA. This part deals with implementation of the QDR II+ controller in popular FPGAs using standard IP blocks.

Implementation of memory interfaces on FPGAs, especially for high-speed memories, was a tedious process until most of the FPGA vendors started providing configurable memory controller IP, such as the Xilinx Memory Interface Generator (MIG) tool and Altera's QDR controller Megacore functions. These IP libraries are expensive and are not available with all variants of the FPGAs, however. Fortunately, alternatives exist. Most high-speed FPGAs offer standard IP blocks that can be configured and integrated to build a custom memory controller. This enables designers to develop memory controllers for their application and allows them to customise it suitably. Understanding the timing diagram of QDRII+ is essential for the controller implementation. Let's take a closer look.

Read and write operation of QDR-II+ SRAM
The control signal for read operations is RPS#. A read operation is initiated when RPS# is asserted on the rising edge of K clock. At this edge, the address present on the address bus is latched onto the address registers. Depending on the latency of the device and whether the device is a burst-of-two or a burst-of-four variant, there are some differences in the timing specification.

For burst-of-four devices, once the address is latched by the assertion of RPS# signal, after the specified latency, data will come out on the "Q" bus on four alternate rising and falling edges of the K clock. Because of this, reads cannot be initiated on two consecutive edges of the K clock. The internal logic ignores the second read request for the device.

Burst-of-two devices also have a similar read operation. The address is latched on the rising edge of the K clock when the RPS# signal is also asserted. Data is driven on the "Q" bus on alternate rising and falling edges of the K clock after the specified latency. Burst-of-two devices have a better random transaction rate since read operations can be done on subsequent rising edges of the K clock.

The control signal for write operations is the WPS# signal. Another control signal called BWS# and is used to control byte-wise writes. This control pin helps to selectively write to only one out of multiple bytes in the device. For example, for a X18 device there are two BWS# signals, namely BWS#[0] and BWS#[1]. BWS#[0] acts as the control signal to write to the lower byte of the memory (Bits 0-8) whereas BWS#[1] acts as the control signal to write to the upper byte without affecting the lower byte. These control signals are used to simplify 'read-modify-write' operations to a single-byte write operation.

For burst-of-four devices, write operations are initiated on the rising edge of the K clock along with the assertion of the WPS# signal when an address is given on the "A" lines. On the next rising edge of the K clock, data has to be provided on the "D" lines. Three more data have to be provided on the next three edges of the K clock; therefore, write operations cannot be initiated on two consecutive K clocks.

For burst-of-two devices, write operations are initiated by asserting WPS# on the rising edge of the K clock. At the same edge, data available at "D" bus is latched into the input registers. On the falling edge of the K clock, the address and next data available on "D" bus are latched into the subsequent block of memory. The concept of data forwarding is applicable in burst-of-two devices in which data has to be provided before providing the address.

The memory controller explained here is for QDRII+ burst-of-two device of 2.5 cycles read latency; however, latency and burst length can be adjusted for other QDRII+ devices by modifying the wait states and data enable states. Figure 1 shows read and write operations of QDRII+ B2 device.

Figure 1: Read and write timing diagram for QDRII+ burst-of-two device (2.5 cycles latency).

Clock and data and control signal generation
QDRII+ SRAMs operate on the K and K# input clocks, up to 533MHz. The FPGA driver should be able to generate this high frequency clock. It is important that the K and K# clocks be 180� out of phase. The PLLs inside FPGA can be used to generate K, K#, and the other internal clocks needed to generate address, data, and control signals.

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