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How to interface QDR-II+ synchronous SRAM with high-speed FPGAs (Part 1)

Posted: 26 Sep 2012     Print Version  Bookmark and Share

Keywords:static random access memory  QDR SRAM  FPGA 

Quad data rate synchronous static random access memory (SRAM) is an essential part of next-generation networking equipment operating at higher throughput rates. QDR SRAM offers low latency compared to dynamic random access memory (DRAM). The random transaction rates of QDR SRAM are higher than for DRAM, as well.

QDR SRAM modules are suited for high bandwidth applications and used for look up tables, buffering packets, linked lists, etc. SRAMs are also a popular choice for Level 2 (L2) cache for FPGA-based systems. QDR SRAMs are typically interfaced to application-specific networking processors or high-speed FPGAs. Getting the best performance from both processor and memory requires properly interfacing the two. This article takes a closer look at the challenges and pitfalls, and the techniques to optimise the system.

Basics of QDR-II+ SRAM
The latest offering of QDR SRAMs operate up to 633MHz and are touted to have improved data valid window to enable host processors to capture data easily at high speeds. QDR uses two different input/output (I/O) ports: a read port used to read from the memory and a write port used to write into the memory. There are independent clock domains for the read and write ports. Data is written and read on both the rising and falling edge of a clock (i.e., double data rate). Four data items are transmitted per clock cycle, and hence are called quad data rate memories.

Let's review the hardware details of interfacing the QDR-II+ SRAM with an FPGA. QDR-II+ SRAMs are available in densities from 18 Mb to 144 Mb. They are internally organised as having two or four blocks. These are available as burst-of-two or burst-of-four devices; the names indicate the minimum number of data words that can be written to or read from the memory in a single transaction.

Consider a QDR-II+ SRAM with 18 Mb density and having 18 data lines. This means it is organised as 1 Mb ×18. For a burst-of-two device, 36 bits of data can be written and read in a single transaction (i.e., at the same time). For a burst-of-four device, 64 bits of device can be read and written in a single transaction. Internally for a burst-of-two device, there are two blocks of memory which are 512 K ×18 each and for a burst-of-four device, internally there are four blocks of memory which are 256 K ×18 each.

The number of address lines for the burst-of-two devices is 19 and the number of address lines for the burst-of-four device is 18 (figure 1). Both devices have 18 data lines for writing into the device and 18 separate data lines for reading from the device. The address is indicated by "A," the write port is indicated by "D," and the read port is indicated by "Q."

Figure 1a: Block diagram of 18 Mb (1 Mb ×18) QDR-II+ burst-of-two SRAM.

Figure 1b: Block diagram of 18 Mb (1 Mb ×18) QDR-II+ burst-of-four SRAM.

Power requirements
The main power requirements for the SRAM are Vdd and Vddq. Vdd is the core power of the system. This is used to power up the core of the memory and is used to keep the contents of memory intact. Vddq is the I/O power and is responsible for input/output transactions. The voltage levels on the output lines are a function of the I/O power. Typically for high-speed systems, the core voltage and I/O voltage are different.

Over the last few years, there has been a drastic reduction in operating voltage to save power. Having different core and I/O voltages ensures that the high switching noise from the I/O will not affect the core voltage. Proper bypassing and decoupling techniques have to be used to ensure proper power integrity of the system. This is very important for reliable operation, especially when the memory is located far away from the power supply on the board and the same power supply is used to power multiple chips in the design. A decoupling capacitor prevents voltage swings on power and ground lines, gives low impedance path from power to ground plane, and provides a return path between power and ground planes.

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