Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Power/Alternative Energy
Power/Alternative Energy  

Understanding power awareness in RTL design analysis

Posted: 18 Sep 2012     Print Version  Bookmark and Share

Keywords:Common Power Format  Unified Power Format  power intent 

With the abundance of mobile and consumer applications redefining the requirements for designing chips for low power requirements, designers have to be aware of power intent formats such as Si2's Common Power Format (CPF) and Accellera's IEEE1801 Unified Power Format (UPF) to define and capture power intent for design implementation and verification. Designing and analysing low power management in chip designs can best be accomplished at RTL, where designers adopt these formats to implement low power strategies like voltage and power islands. In this article, we will discuss several approaches on how these formats play a key role in capturing power intent for RTL design analysis and verification.

Power-intent aware CDC analysis
Clock domain crossing (CDC) verification ensures that proper synchronisation has been done for all asynchronous clock crossings in the design. Else, these crossings can cause metastability in the design and can lead to functional failure in the chip. Typically, exhaustive CDC verification is done at the RTL stage and handed off to design implementation. As part of low power implementation, isolation logic is inserted by synthesis tools at the gate level to isolate the power domain outputs when the domain is powered off. Isolation logic is used to ensure that unknown signals do not propagate to downstream logic and cause electrical problems.

Figure 1: Isolation logic insertion at gate level causing metastability issues.

This isolation logic insertion at the gate level may now lead to un-synchronised crossings. Figure 1 illustrates the problem. In this circuit, there is power domain crossing from a switched off domain PD to an always-on domain VD, where the crossing between S and D registers are synchronous. Hence, there is no CDC issue with this circuit.

The power intent has been described in UPF to capture the domain information as well as the isolation strategy such that the synthesis tool can insert the isolation cell to isolate the PD output signal to a known value during the power shut down. However, due to the isolation logic insertion, a new logic path has been created, which in fact is a clock domain crossing (C2->C1, C1, C2 are asynchronous clocks). This crossing requires additional synchronisation, which was not done at the RTL stage. Detecting such crossings is only possible by analysing the RTL with power intent awareness. Otherwise, they may be detected late in the design process, which causes painful surprises or even chip failures. Based on the complexity of changes involved, re-iteration of Synthesis/P&R is needed, which can adversely impact design schedules.

Power-intent aware DFT analysis
It's very important to ensure that circuits are correctly designed for manufacturing test. The correct insertion of design for test logic (DFT) helps effective operation of ATPG tools to generate test patterns for high test quality. Let us take the same circuit in figure 1, we discussed for CDC analysis. In this circuit, if the register "EN" has been changed to a scan flip-flop by synthesis, then during scan shift mode, the isolation enable signal value can change from 1->0. This will isolate the power domain outputs but the logic at register "S" cannot be testable. The same issue is also applicable to power switch control signals as well as retention control logic. So, an additional test circuit needs to be added for low power cells such as isolation, retention and power switches. Hence, it's very critical to perform power aware DFT analysis during the early design stages, preferably at RTL.

Figure 2: CPF example for synthesis and physical design implementation.

Power-intent aware timing analysis
In figure 2, the power intent is captured in CPF which defines multiple voltage domains Vtop, V1 operating at 0.8V and 0.6V respectively. To meet the timing in the V1 domain, the cells in the critical path need to have higher drive strength or additional buffers need to be added for timing optimisation. However, if timing analysis is performed without the awareness of power, then timing will not be met and may need many synthesis iterations. So, it's essential to perform power aware timing analysis for multi-voltage designs. This is not only useful for timing but also impacts area as higher drive strength cells have higher area.

1 • 2 Next Page Last Page

Comment on "Understanding power awareness in RTL..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top