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Fujitsu taps Cadence signoff for ref design flow

Posted: 20 Jul 2012     Print Version  Bookmark and Share

Keywords:reference design flow  signoff  ECO 

Fujitsu Semiconductor Ltd adopted the Cadence Encounter Timing System for timing signoff after evaluating comprehensive competitive benchmark across a series of ASIC/ASSP and SoC designs.

Using Cadence technology, Fujitsu Semiconductor said that 99 per cent of hold violations were resolved after just one iteration through the ECO flow. In addition, negligible impact was made to setup time, and better routability was achieved when compared to another vendor's signoff product. Cadence Encounter Timing System is said to have delivered comprehensive physically-aware, multi-mode, multi-corner (MMMC) analysis across the design flow, engineering change orders (ECOs), and final signoff.

Timing signoff closure has become an increasingly significant bottleneck due to the increase in modes and corners required for analysis and the divergence of timing results between implementation and signoff timing tools. Furthermore, the complexity of today's designs requires the ability to do complete physically-aware MMMC signoff during ECO for rapid timing closure. To accomplish this requires a deep integration between physical and signoff design tools and a fundamentally new approach to software architecture. All of this can be done today uniquely with Cadence Encounter Timing System. The Encounter Timing System's physically aware timing ECO met Fujitsu's qualification criteria, and was incorporated into its production reference design flow.

Cadence Encounter Timing System and QRC Extraction are essential elements within the design implementation environment. The tight integration between them improves timing convergence throughout the design flow and greatly reduces time to design closure. While traditional flows require a serial, multi-step iterative process between physical implementation and signoff, the integrated signoff technology inside the Cadence digital implementation flow enabled Fujitsu Semiconductor to reduce the number of ECO loops due to deterministic placement of new cells while optimising performance and area for its large, high-performance designs.

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