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IP core eases 40GbE, 100GbE Ethernet connections

Posted: 18 Jul 2012     Print Version  Bookmark and Share

Keywords:Ethernet  IP cores  MAC  PHY 

Altera Corp. rolls its 40GbE and 100GbE IP cores for building systems that need very high throughput-rate standard Ethernet connections, including chip-to-optical module, chip-to-chip, and backplane applications. The MAC and PHY coding sub layer plus physical media attachment (PCS+PMA) sub layer IP cores are IEEE 802.3ba-2010 standard compliant.

The IP cores are said to reduce design complexity for customers who need to integrate 40GbE and 100GbE connections on Altera's 28nm Stratix V FPGAs and 40nm Stratix IV FPGAs. With them, Altera is enabling the system-level throughput promise of 40GbE/100GbE and raising the level of design abstraction for FPGA designers while boosting design team productivity.

The 40GbE and 100GbE MAC and PHY IP cores provide an interface composed of a single packet-based channel that is logically compatible with previous-generation Ethernet systems. The cores are supported in Altera's Stratix V GT and GX FPGAs with transceivers operating at data rates up to 28.05Gbit/s and 14.1Gbit/s, respectively, and Stratix IV GT FPGAs with transceivers operating at data rates up to 11.3Gbit/s. Stratix FPGAs combine high density, high performance and a rich feature set, allowing customers to integrate more functions and maximise system bandwidth.

Altera's 40GbE and 100GbE IP cores are available for separate download from and are compatible with the recently announced Quartus II software v12.0.

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