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Cadence enhances PCIe verification IP

Posted: 16 Jul 2012     Print Version  Bookmark and Share

Keywords:verification  IP  PCIe 

Cadence Design Systems Inc. demonstrates the new capabilities of its PCIe Verification IP (PCIe VIP). Said to result in more in-depth verification of the most current PCIe specification at the block and SoC levels, the verification tool supports the new PCIe PIPE4 specification.

Specifically, it offers performance measurement features critical for optimising PCIe implementation; TripleCheck test suite, coverage and verification plan to shorten and ease testing for full PCIe specification compliance; and Accelerated PCIe VIP that drives the verification speed required for large SoCs.

The tool addresses the full spectrum of PCIe applications and supports the latest specifications, including SR-IOV, MR-IOV, NVMe and PIPE4, empowering customers to implement designs quickly and confidently incorporating the newest PCI Express interfaces, said the company.

Already used on hundreds of production designs, the Cadence PCIe VIP enables efficient and thorough verification of SoCs. A new performance measurement utility helps customers optimise their designs for improved link utilisation, throughput, latency, and power.

The PCIe TripleCheck IP Validator, Cadence's third-generation compliance solution, verifies that IP blocks comply fully with protocol specifications. TripleCheck combines the three most critical components of verification in a single, easy-to-use environment: a test suite, coverage model, and verification plan covering all sections of the PCIe specification including PL, DLL, TL, Power Management and Error Handling—all of which are automatically customised to the user's individual configuration. This level of testing is critical to ensure that IP components will function in all of the intended SoC applications.

The Accelerated VIP gives a 100x boost in simulation throughput of Universal Verification Methodology (UVM)-compliant test benches using the Cadence Palladium XP verification computing platform. This simulation-acceleration usage mode lets users perform full-chip simulation that would otherwise be impossible or impractical in RTL simulation alone.

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