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Xilinx launches Vivado Design Suite

Posted: 03 May 2012     Print Version  Bookmark and Share

Keywords:FPGA design  programmable systems  3D stacked silicon interconnect technology 

Xilinx has launched 'Vivado Design Suite' – an IP and system-centric design environment that will accelerate design productivity. The FPGAR claims that Vivado can accelerate programmable systems integration and implementation by up to 4X.

According to the company, the tools are intended to "not only speed the design of programmable logic and I/O, but accelerate programmable systems integration and implementation into devices incorporating 3D stacked silicon interconnect technology, ARM processing systems, analogue mixed signal and a significant percentage of semiconductor intellectual property (IP) cores."

"Vivado tools are the culmination of work started by Xilinx engineers in 2008. In response to customers' needs for more productivity, faster time to market, and the ability to go beyond programmable logic to programmable systems integration, a new design environment was required."

The ISE Design Suite, version 14, does support today's 28 nm devices and Xilinx said it will continue to support the tools for designs targeting previous generation devices. But for future generation devices beyond 28nm, Vivado will be the only tool.

Vivado provides an integrated design environment with a new generation of system-to-chip level tools, built on a shared scalable data model and a common debug environment. It is also an open environment based on industry standards, such as the AMBA4 AXI4 interconnect, IP-XACT IP packaging metadata, the Tool Command Language, and Synopsys Design Constraints.

Xilinx architected Vivado to enable the combination of all types of programmable technologies and scale up to 100 million ASIC equivalent gate designs.

The Vivado IDE includes electronic system level (ESL) design tools for rapidly synthesising and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems with 3X faster simulation, while hardware co-simulation provides 100X more performance, claims Xilinx.

The tools include a hierarchical device editor and floor planner with support for SystemVerilog, and a 4X faster more deterministic place and route engine. In addition, incremental flows allow for engineering change order (ECO) induced changes to be quickly processed by only re-implementing a small part of the design.

The Vivado Design Suite version 2012.1 is available as part of an early access programme. Public access will commence with version 2012.2 early this summer, followed by WebPACK availability and Zynq-7000 extensible processing platform (EPP) support later in the year.

ISE Design Suite Edition customers with current support will be provided the new Vivado Design Suite Editions in addition to ISE at no additional cost. Xilinx will be offering this design tool for about Rs.1.02 lakh ($2000).

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