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Implement POSIX IPC on Cortex-M architectures

Posted: 17 Apr 2012     Print Version  Bookmark and Share

Keywords:32bit microcontroller  Cortex-M3  context switching  inter-process communication 

The ARM Cortex-M architecture is a 32bit microcontroller core designed to take over many 8bit and 16bit devices. This is in contrast to the ARM Cortex-A architecture, an application processor that typically runs Linux, iOS, or Windows 8 (at least in development environments).

The M-series runs lesser-known, embedded operating systems such as FreeRTOS, ThreadX, and my favourite (of course) CoActionOS. These operating systems use the advanced features of the Cortex-M architecture to implement system functionality such as context switching and inter-process communication (IPC).

This article explains how to implement the system components required to send and receive POSIX-style signals—a form of IPC—between concurrently running tasks on the Cortex-M architecture, and deals specifically with the Cortex-M3 (CM3).

Processor interrupt vs. task interrupt
A processor interrupt, when talking in general about interrupts on microcontrollers, is usually triggered by peripheral circuitry such as a timer or input/output port, and causes the processor to suspend its current activities and execute an interrupt service routine (ISR). On the CM3, the Nested Vectored Interrupt Controller (NVIC) handles processor interrupts. By contrast, a task interrupt is when a function is placed on a dormant task's stack and executed when the task resumes.

For purposes of this discussion, a 'task' is defined as an independent execution context (either a process or thread) that is preemptively managed by a scheduling algorithm. An example of a task interrupt in a POSIX-style operating system is when a task calls the sigqueue() or kill() function. The operating system inserts a function on the stack of the task receiving the signal. When the scheduler resumes execution of the receiving task, the signal handling function is executed before the task resumes.

On the CM3, a processor interrupt has two attributes that make task interrupts useful. First, the CM3's NVIC always executes ISRs in handler mode rather than process mode. Second, ISR execution is prioritized over normal execution. Using a task interrupt allows application developers to execute the response to an event in process mode and at the same priority level as the task that is responding to the event.

System support hardware, context switching
Note: To implement task interrupts on the CM3, knowledge of advanced CM3 features as well as context switching is required.

Advanced features of the CM3 include two execution modes and two stack pointers. The execution modes are handler mode and process mode while the stacks are the main stack pointer (MSP) and the process stack pointer (PSP). ISRs always execute in handler mode: privileged and using the MSP. Process mode can be configured to use either the MSP or the PSP as well as to be privileged or unprivileged. Unprivileged code execution has limited access to critical system registers.

Additionally, the memory protection unit (MPU) can be configured to allow privileged software to have different permissions than unprivileged code. Code executing in process mode must use the SVCall interrupt to switch to handler mode; this allows application developers access to kernel features such as context switching.

The CM3 architecture provides two processor interrupts that facilitate context switching: the PendSV and SysTick interrupts. The PendSV interrupt can be triggered by software while the SysTick interrupt is triggered when the SysTick timer counts down to zero. One systems design approach is to use PendSV for FIFO algorithms and SysTick for round robin scheduling.

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