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Imec teams up with HiSilicon

Posted: 29 Feb 2012     Print Version  Bookmark and Share

Keywords:RF transceiver  CMOS  nanoscale transistors  analogue-to-digital converters 

Imec and HiSilicon have announced research collaboration to develop innovative RF transceiver architectures for next-generation mobile terminals. With the partnership, HiSilicon joins Imec's R&D programme on cognitive reconfigurable radio to jointly conceive low-power and compact high-performance reconfigurable RF transceivers leveraging on state-of-the-art CMOS technology.

Imec's cognitive reconfigurable radio front-end programme investigates reconfigurable RF solutions, high-speed/low-power analogue-to-digital converters (ADCs) and new approaches to digitise future RF architectures and minimise antenna interface requirements.

"By combining fundamental rethinking of the circuit architectures and designs with clever use of the benefits that the aggressively scaled technology offers (such as high intrinsic speed of the nanoscale transistors) the programme aims at developing small, cost-, performance- and power-competitive reconfigurable radio transceivers in 28nm digital CMOS technology covering all key broadband communication standards including next generation cellular and connectivity standards such as LTE advanced and next-generation WiFi (802.11ac)," the research institute stated.

"We are excited to welcome HiSilicon as one of the world's leading IC design companies and we are honoured with this commitment," said Liesbet Van der Perre, director, Green Radio programme line, Imec. "We are looking forward to a close cooperation with the HiSilicon research team to develop together our upcoming generation of breakthrough RF designs."

Chen Zhen, director, HiSilicon wireless chipset infrastructure architecture and system design dept., added, "We expect imec to keep on bringing innovative solutions that will be essential to develop our next generation multi-mode products. We hope that together with imec, we will realise innovative transceiver architectures utilising the advantages of new technologies (28nm CMOS and beyond). We expect these solutions can drastically improve the performance while reducing area and power consumption."

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