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Synopsys IP optimises 28nm SoC performance

Posted: 16 Feb 2012     Print Version  Bookmark and Share

Keywords:IP  28nm  HPM 

Synopsys Inc. reveals the immediate availability of DesignWare Embedded Memory and Logic Library IP for TSMC's 28nm high-performance (HP) and high-performance for mobile (HPM) process technologies.

The Synopsys DesignWare Embedded Memories and Logic Libraries are designed to deliver high performance with low leakage and active power, giving engineers the ability to optimise their entire system-on-chip (SoC) design for speed and energy efficiency, according to the company. In combination with the embedded test and repair technology of the DesignWare STAR Memory System, Synopsys' embedded memories and standard cell libraries offer designers an advanced, comprehensive IP solution for creating high-performance, low-power 28nm SoCs with reduced test and manufacturing costs.

The new DesignWare IP extends Synopsys' broad portfolio of high-speed, low-power memories and standard cell libraries currently supporting a range of foundries and processes from 180nm to 28nm. DesignWare 28nm Logic Libraries take advantage of multiple threshold variants and gate length bias combinations to deliver optimal performance and power results for a wide variety of SoC applications. These libraries offer multiple, synthesis-friendly cell sets and router-friendly standard cell library architectures designed for multi-GHz performance with minimal die area and high manufacturing yield. Power Optimisation Kits (POKs) provide designers with advanced power management capabilities supported by popular low-power design flows, including shut-down, multi-voltage and dynamic voltage frequency scaling (DVFS).

The combination of high-speed, high-density and ultra-high-density DesignWare Embedded Memories gives designers the flexibility to make performance, power and area trade-offs for each memory used in their SoC, according to Synopsys. For power-sensitive applications such as mobile devices, all of Synopsys' 28nm memories incorporate source biasing and multiple power management modes that significantly reduce leakage and dynamic power dissipation. Synopsys' ultra-high-density two-port SRAM and 16Mb single-port SRAM compilers further reduce area and leakage by up to 40 per cent compared to standard high-density memories, enabling SoC developers to implement memories with a differentiated blend of high performance, small area and extremely low power.

The DesignWare Embedded Memories and Logic Libraries for TSMC's 28HP and 28HPM processes are part of the DesignWare Duet Package, which includes SRAMs, ROMs, standard cells, Power Optimisation Kits (POKs) and optional overdrive/low voltage PVTs. The Duet Package for TSMC's 28HP and 28HPM processes is available now.





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