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2.5GHz multi-core processors boost performance

Posted: 15 Feb 2012     Print Version  Bookmark and Share

Keywords:embedded SoC  multi-core processor  data centre 

Cavium Inc. debuts the MIPS64 2.5GHz OCTEON III multi-core processors, a family of 1-48 core processors that are said to deliver more than 100Gb/s of application performance per chip allowing for linear scaling across multiple chips.

The MIPS64 2.5GHz OCTEON III multi-core processors provide 120GHz of 64bit compute processing per chip offering up to 4x higher application performance than OCTEON II with superior performance per watt, according to the company.

OCTEON III integrates search processing from Cavium's NEURON search processors with 5th generation DPI acceleration, dramatically reducing BOM cost and power, indicated Cavium. The embedded multi-core processor line is designed into enterprise, data centre and service provider equipment including routers, switches, appliances, 3G/4G wireless base stations, RNCs, xGSNs, evolved packet core, services gateways, DPI equipment, storage switches and intelligent server adapters.

The OCTEON II includes core-architecture enhancements, larger caches and short, efficient pipelines to deliver lower-latency, greater determinism and superior performance/watt than alternative 'Pseudo-Core' solutions. It also provides access to a large, highly associative L2 cache running at full core-frequency that results in substantially lower latency for packet processing when compared to three level cache architectures that typically operate at a fraction of core-frequency, noted Cavium.

The low latency coherency architecture of the device enables multiple OCTEON III chips to appear as a single logical high-performance processor with up to 384 cores. This provides up to 960GHz compute, up to 800+ Gb/s of application performance and up to 2TB of memory capacity at lower latency versus alternative solutions, explained the company. Traffic arriving at any chip can be processed by any other chip, without the data first having to be written to the local memory of the first chip.

The multi-core processor likewise features more than 500 dedicated hardware engines for packet processing, quality of service (QoS), security, compression and deep packet inspection. It boasts the highest L2-L7 packet processing including hardware acceleration of packet forwarding, IPsec, security, TCP and DPI applications at up to 100+Gb/s in a single chip. In addition, it delivers compression/decompression performance of up to 50+Gb/s in a single chip.

OCTEON III has more than 500Gb/s of I/O connectivity per chip that include multiple ports of 40G, 20G, 10G, GE, Interlaken, Interlaken/LA, SRIO, PCIe Gen3, SATA 6G and USB 3.0. Moreover, it has on chip 4x 72b DDR3/4 memory controllers delivering more than 600Gb/s of memory bandwidth. Also, its granular power management technology provides up to 4X performance per watt compared to OCTEON II, continued Cavium.

The processor family is accompanied by Cavium's software development kit (SDK), hardened APIs and software stacks for networking, security and storage applications. Cavium's SDK offers simplified multi-core development by providing support for standard OS, GNU tool-chains, C/C++ based software applications, advanced debugging/profiling tools such as Oprofile, Valgrind, Cachegrind and production quality APIs and software stacks.

The 28nm OCTEON III silicon is expected to sample in 2H12.





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