Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Manufacturing/Packaging

A look at Micro SMDxt wafer level CSP

Posted: 21 Feb 2012     Print Version  Bookmark and Share

Keywords:wafer level  chip scale packaging  footprint 

Micro SMDxt is a wafer level chip scale packaging (WLCSP). Some of its features are:

 • Package size equal to die size
 • Smallest footprint per I/O count
 • No need for underfill material
 • Interconnect layout available in 0.4 mm or 0.5 mm pitch
 • No interposer between the silicon IC and the printed circuit board

This application note shows typical micro SMDxt products. They have solder bumps located on the active side of silicon IC. The micro SMDxt manufacturing process steps include standard wafer fabrication process, wafer re-passivation, deposition of solder bumps on i/o pads, application of protective encapsulation coating, testing using wafer sort platform, laser marking, singulation and packing in tape and reel. The package is assembled on PCB using standard surface mount assembly techniques (SMT).

View the PDF document for more information.

Originally published by Texas Instruments at as "Micro SMDxt Wafer Level Chip Scale Package".

Comment on "A look at Micro SMDxt wafer level CS..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top