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Cadence, Samsung collaborate on DFM solution

Posted: 07 Feb 2012     Print Version  Bookmark and Share

Keywords:20nm  DFM  SoC 

Samsung Electronics' Foundry business, Samsung Foundry, has collaborated with Cadence to develop a world-class design-for-manufacturing (DFM) infrastructure to produce the most advanced chips.

Cadence and Samsung Foundry have jointly developed "in-design" and signoff DFM flows to tackle physical signoff and electrical variability optimisation for 32-, 28- and 20nm SoC designs.

"The new flows address both random and systematic yield issues, providing customers with a proven foundry option for advanced-node designs built on the Cadence Encounter digital and Cadence Virtuoso custom/analogue implementation solutions."

The DFM flows developed at Samsung Foundry leverage multiple technologies, including Cadence Pattern Classification and Search, Cadence CMP Predictor, Cadence Litho Physical Analyser and Cadence Yield Analyser and Optimiser.

"As we expand our customer base at advanced process nodes, customers require various design flows," said Kyu-Myung Choi, senior vice president of Infrastructure Design Center, Samsung Electronics, "By teaming with Cadence to build a strong foundry ecosystem for advanced node designs, we've achieved numerous benefits we can pass along to our customers such as reducing risk and speeding time to market. We've enjoyed great success at 32 and 28nm with Cadence, and we have now extended our advanced DFM flow to 20nm as well."

The Cadence pattern classification technology allows Samsung Foundry to classify the yield detractor patterns into usable pattern libraries. The infrastructure enables Samsung Foundry's customers to leverage the in-design and signoff pattern matching with automated fixing flows in Encounter and Virtuoso.

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