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How to employ critical area analysis

Posted: 20 Jan 2012     Print Version  Bookmark and Share

Keywords:design-for-manufacturing  Critical area analysis  Memory redundancy 

The goal of reducing a design's sensitivity to manufacturing issues should always ideally be handled by the design teams whether you are fabless, fab-lite, or IDM. The farther downstream a design goes, the less likely a manufacturing problem can be addressed without costly redesign. By addressing design-for-manufacturing (DFM) problems early, when the design is still in progress, manufacturing ramp-up issues can be avoided.

One aspect of DFM is determining how sensitive a physical design (layout) is to random particle defects. The probability of a random particle defect is a function of the spacing of layout features, so tighter spacing increases random defects. Because memories are relatively dense structures, they are inherently more sensitive to random defects, so when they are embedded in an SOC design, they can impact the overall yield of the device.

CAA for embedded memory
Critical area analysis (CAA) is a DFM technique that measures the susceptibility of a specific layout to random defects and indicates areas of the layout where design modifications can have the greatest positive impact on overall yield. One way to improve yield of an SOC design with embedded memory is to increase the layout spacing in some areas to achieve a better CAA score. Another way is to build redundancy into the memory design so faulty cells can be bypassed during final production test. Of course, redundancy also has a cost in terms of real estate. So deciding how much to employ DFM techniques versus adding more redundant cells is an engineering optimisation problem.

Understanding how to employ CAA becomes more important at each successive node. Memories just keep getting bigger and smaller dimensions introduce new defect types. The trade-offs that have worked well on previous nodes may not give optimal results at 28 nm. For example, although row redundancy has been avoided in the past because it has been considered too costly in terms of access time, at 28 nm it may be required to achieve acceptable yields. All of these factors make careful analysis more valuable as a design optimisation tool.

Figure 1: Definition of critical area. For shorts the critical area (red) is area of the layout where a particle of a given size can cause a short. For opens, it is the area where a particle can cause an open.

Background on CAA
Critical area is the area of a layout where a particle of a given size will cause a functional failure. Critical area depends only on the layout and the range of particle sizes being simulated. CAA calculates values for the expected Average Number of Faults (ANF) and yield based on the dimensions and spacing of layout features and the particle size and density distribution measured by the fab (figure 1). In addition to classic shorts and opens calculations, current practice in CAA is to include via and contact failures in the analysis. In fact, after analysis, it is often the case that via/contact failures are the dominant failure mechanism. Other failure mechanisms may also be incorporated into the analysis, depending on the defect data provided by the fab.

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