Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Manufacturing/Packaging

Managing single event effects in FPGAs, ASICs and processors (Part 1)

Posted: 28 Dec 2011     Print Version  Bookmark and Share

Keywords:single-event effects  ASICs  FPGAs  single-event latch-up 

Note: The SRAM cells used for the configuration memory of FPGAs should be larger and more robust than the SRAM cells used for general-purpose memory, which are optimised for speed and cost. Moreover, configuration memory cells should be optimised for SEU resistance.

SEE concerns in ASICs
SEE concerns in ASICs have risen because of the decreased operating voltages and element capacitance combined with increased clock speeds. These factors mean that transient upsets are more likely to occur and can easily translate to clocked functional errors. SERs can now easily exceed 50,000 FIT per processor, including logic gates and on-chip memory. System-level consideration and mitigation techniques are necessary for ASICs.2 Other data shows that ASIC designs below 90 nm have exhibited 1,000 FIT per million gates, and 1,000 FIT per million memory bits.3 User memory can be protected, but logic upsets, which can account for a substantial portion of the upset rate, cannot be easily protected. Logical SETs, when latched, can lead to logic errors and consequently are no longer negligible in processors manufactured on deep subµm processes. System-level solutions are required.4

At the same time that ASICs have become more susceptible to upset, some FPGAs have been designed for improved immunity and lower soft error FIT rates. In fact, Xilinx devices at 65 nm and below have shown improved immunity, with nominal rates on the order of less than 100 FIT/Mb for configuration memories and below 500 FIT/Mb for user memories.5

For both ASICs and FPGAs, there are non-zero error rates, non-zero detection times, and non-zero correction times. It is imperative to consider SEEs both when using ASICs and when using FPGAs in any high-reliability application. Designers should seek vendors that provide information to assist them in analysing system FIT rates and estimating the FIT rate for their targeted device.5,6 Exact processor FIT rates can also be tricky to determine, requiring a combination of analysis, simulation, and beam testing.

Beyond vendor data, some airframe manufacturers have SEE models or estimations that they apply and levy broadly across multiple vendors' technologies. This approach provides a rough estimate for those vendors that do not supply data, but this approach is risky. Products fully tested and characterized provide a safer solution.7

SEE rates are probabilistic and vary with geographic location, environmental conditions, and altitude. All FIT rates are estimates based on modelling, analysis, and/or testing, but not all published FIT rates are created equal. It is important that data comply with the JEDEC Standard 89A (JESD89A), which Xilinx played a role in updating.6 The Xilinx FIT rate calculator applies the models from JESD89A with FPGA FIT rate data to yield an adjusted, application-specific FIT rate.

All radiation testing is not created equal either. Particle test beams can vary in their energy and particle, for example. To counteract this variability, companies need to use control devices when conducting beam testing to adjust for test setup and beam variation from run to run. Flight tests can capture real-world data regarding FIT rates, but geographic location and timing with the solar activity can cause variability in the data. Ultimately, soft-error FIT rates are estimates that enable the developer to assess the probability of fielded system upset rates.

Systems that utilise sub-90 nm geometries, products like ASICs and FPGAs, in any avionics or high-reliability application must adopt proper techniques to mitigate the susceptibility of such technologies to SEEs. In part two of this article, we will discuss approaches to mitigate the effects of SEEs.

1. "NSEU Mitigation in Avionics Applications," Xilinx application note XAPP1073 (2010).
2. Robert Baumann, Soft Errors in Advanced Computer Systems, IEEE Copublished by the IEEE CS and the IEEE CASS (2005).
3. "Xilinx FPGAs Overcome the Side Effects of Sub-90 nm Technology," Xilinx whitepaper WP256 (2011).
4. Rebaudengo, Reorda, et al., "Coping With SEUs/SETs in Microprocessors by Means of Low-Cost Solutions: A Comparison Study, IEEE Transactions on Nuclear Science (2002).
5. UG116, Device Reliability Report
6. "Continuing Experiments of Atmospheric Neutron Effects on Deep Sub-micron Integrated Circuits," Xilinx whitepaper WP286 (2011).
7. Xilinx Space website

About the author
Dagan White has over 15 years of multi-disciplinary engineering experience within the A&D industry. His electronics and systems development work has spanned mixed-signal electronics hardware design and FPGA development for lidar systems and radiometers. He has worked for Lockheed Martin Coherent Technologies and ITT Geospatial Systems, and is now with Xilinx as staff systems architect for avionics, tasked with leading FPGA avionics solutions development; current areas of focus include DO-254, SEU, IP, and design flows. Dagan holds a BSEE and an MBA from the University of Colorado.

To download the PDF version, click here.

 First Page Previous Page 1 • 2 • 3

Comment on "Managing single event effects in FPG..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top