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Managing single event effects in FPGAs, ASICs and processors (Part 1)

Posted: 28 Dec 2011     Print Version  Bookmark and Share

Keywords:single-event effects  ASICs  FPGAs  single-event latch-up 

In high-reliability system development, single-event effects (SEEs) are of a growing concern, yet there is much disparity among users of application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) with regard to understanding how susceptible their designs might be. The avionics and industrial system development guidance that currently exists is only broadly beginning to consider SEEs and their impact on system reliability. Unfortunately, standards such as DO-254, DO-178, ARP 4754, ARP 4761, and IEC 61508 provide little or no direction on how to handle SEEs. This white paper highlights concerns regarding effects of SEEs on ASICs and FPGAs and points to analysis and mitigation techniques for handling SEEs.

All sub-micron integrated electronics devices are susceptible to SEEs to some degree. The effects can range from transients causing logical errors, to upsets changing data, to destructive single-event latch-up (SEL). Traditionally, FPGAs were targeted as being more sensitive due to their use of SRAM for the configuration storage. As dimensions shrink to below 90 nm, SEEs in all devices, including ASICs, FPGAs, and application-specific standard products (ASSPs) must be considered.

Although targeted to an avionics audience, this article has broad applicability to any industry in which safety and reliability are of critical importance. It should be useful to a wide audience comprised of system architects, engineering and program managers, and certification authorities.

SEE phenomenon
SEEs result from interaction of high-energy particles with circuit elements in integrated circuits. When a high-energy particle passes through the silicon substrate of a device, charged particles are created as the result of sub-atomic particle collisions. These particles are generated by an ionisation trail along the path of the incoming particle.

If a charged particle impacts at or near a transistor junction, the collected charge can induce an upset to the state of that transistor. If the collected charge is larger than the critical charge of the element, the element changes state. This change in state (or bit flip, in the case of a memory cell) is referred to as an SEU. Similarly, the charged particles can induce a current and voltage spike on a metal interconnect, which is referred to as a single-event transient (SET). If the pulse width of the spike is wide enough, the spike can propagate through the circuit (see Types of Single Event Effects).

Sources of charged particles
Two sources of charge particles are of concern to designers of high-reliability systems: cosmic ray interactions with the atmosphere, and impurities in packaging materials and the silicon substrate.

Atmospheric sources: Galactic cosmic rays (GCR) originate in outer space, are primarily comprised of subatomic particles and light ions, travel at nearly the speed of light, and strike Earth from all directions. As high-energy cosmic rays enter the atmosphere and react with atoms, through a process known as direct nuclear spallation, neutrons are generated in the atmosphere. The result of this phenomenon is often referred to as an air shower. Neutrons with energy greater than 10 MeV carry sufficient energy to cause SEEs in integrated circuits.

Atmospheric depth (density) also plays a significant role in causing neutron-generating reactions and in transporting neutrons to ground level. An intense neutron environment exists at higher altitudes in the atmosphere, 10 km to 40 km and more above the surface. In addition, Earth's magnetic field causes the flux to vary from the equator to the poles, with the equator having the least flux and the poles having the greatest flux. The magnetic field of the sun as it varies during the sunspot cycle also influences the flux of cosmic rays; maximum flux occurs at a solar minimum, for example.1

Packaging material impurities: Packaging materials used for integrated circuits often contain impurities, including trace amounts of uranium and thorium isotopes, which emit alpha particles as they decay. Although these particles are low in energy and have limited penetration depth, they are a concern for integrated circuits due to their close proximity to the silicon substrates.

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