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Shift from FPGAs for prototype to ASICs for production

Posted: 16 Dec 2011     Print Version  Bookmark and Share

Keywords:FPGAs  ASICs  non-recurring engineering 

Synchronous design techniques: A synchronous design can be ported to any technology node, providing it meets system performance requirements. A completely synchronous design is one that has a single master clock and a single master set/reset driving all sequential elements in the design. All input signals are synchronised to the clock so they never violate setup and hold times. Not many designs meet this rigid definition and often designs require multiple clock domains. Great care must be taken to synchronise data transfer between these domains by using either a handshaking protocol or first-in-first-out (FIFO) techniques. Gated clocks should be avoided unless low power requirements drive their implementation. If gated clocks must be used, designers should work closely with the ASIC vendor to prevent any potential glitches being generated on the clock lines. It is also best to think about design for test. Avoid the use of latches and combinational feedback loops and provide the ability to reset all sequential elements.

Packaging: When designing in an FPGA, it is important for the design team to review package requirements and board layout. FPGAs use significantly more power than ASICs and may require a higher-performance package. The FPGA is also less efficient with core logic. If the design is placed into a larger FPGA family to accommodate the core logic requirements, the design may fit into a smaller pin count package once it is migrated to an ASIC. Package costs track with ball count and substrate performance. If the design can utilise a lower-performance industry standard package with lower ball counts, the device cost can be reduced dramatically. A drop-in replacement package can usually be provided, which will minimise any board rework and provide no or limited change to the system for software and hardware.

Information required for conversion: The information required by the ASIC vendor varies depending on the technical requirements of the design. In general, the more information provided, the better picture of the design the ASIC team will have. Minimum requirements include:

 • Intended ambient operating temperature
 • Desired core voltage
 • Pad voltage(s)
 • Specification of inputs, outputs, and bi-directional signals
 • Identification of transceiver requirements such as type (LVDS, HSTL, SSTL, LVPECL), speed, and version
 • Memory (RAM, ROM) requirements
 • IP requirements (all relevant IP information such as name, brief description, quantity, speed, and compatibility to existing standards, vendor, and licensing requirements
 • Usage and purpose of timing IP blocks such as DLLs or PLLs
 • Package type
 • Design format (RTL, Verilog, VHDL, FPGA)
 • Timing requirements
 • Power Budgets

FPGAs provide a fast time-to-market and an efficient prototyping tool, but the high cost of mid-to high-end FPGAs can be prohibitive for volume production. With proper planning during the development phase, migrating the FPGA to an ASIC can be completed quickly without significant additional engineering effort.

1. Reuse Methodology Manual, Michael Keating & Pierre Bricaud, Kluwer Academic Publishers, 1999, IEEE P1364.1 "Draft Standard for Verilog Register Transfer Level Synthesis"

About the authors
Terry Danzer is currently Digital ASIC Product Marketing for the Americas and Asia. Prior to joining ON Semiconductor, Danzer served in the United States Air Force as a technical instructor working on Minuteman-III ICBMs. During his tenure at ON Semiconductor, Terry has worked as digital ASIC design centre manager, design engineer and test engineer. He holds a BSEE from Montana State University.

Cale Entzel is a System Architect in the Digital, MilAero and Image Sensor group at ON Semiconductor where he provides technical support to field sales and customers. Cale has also worked at a test engineer, design engineer, and program manager. He holds a BSEE from Montana State University.

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