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IBM unveils Racetrack memory chip

Posted: 07 Dec 2011     Print Version  Bookmark and Share

Keywords:Racetrack  memory device  nanowires  hard drives 

At the IEEE International Electron Devices meeting this week, IBM unveiled a prototype 'Racetrack Memory'. IBM claims it a high performance, non-volatile memory device based on the controlled motion of magnetic domain walls in nanowires using pulses of spin-polarized current.

Developed using the standard chipmaking process, Racetrack memory combines the benefits of magnetic hard drives and solid-state memory to overcome challenges of growing memory demands and shrinking devices.

Integrated with CMOS technology on 200mm wafers, IBM's Racetrack memory device was demonstrated to read and write on an array of 256 in-plane, magnetized horizontal racetracks.

"This development lays the foundation for further improving Racetrack memory's density and reliability using perpendicular magnetized racetracks and three-dimensional architectures."

"This breakthrough could lead to a new type of data-centric computing that allows massive amounts of stored information to be accessed in less than a billionth of a second," the company said.

"Racetrack memory is one of a number of new technologies aiming to replace flash memory, and potentially offer a "universal" memory device applicable to a wide variety of roles."





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