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Optimising software using TLM virtual platform

Posted: 07 Dec 2011     Print Version  Bookmark and Share

Keywords:transaction level modelling  system model  software 

An aerospace electronics company was required to quantify the performance of their customers' embedded code running on one of their delivered systems. They were able to successfully accomplish this goal by using a transaction level modelling (TLM) 2.0 methodology to produce an executable system model and, subsequently, execute software to analyse functional aspects contributing to overall system level performance.

The platform they needed to analyse was a multi-board system that processes incoming data packets. Onboard timers were used to synchronise data frames and initiate CPU processing via interrupts. The CPU must process a packet before the next packet is acquired in order to maintain real time. The time from when the CPU finishes processing a packet until the arrival of the next packet is defined as CPU idle time. If enough idle time exists, then additional capabilities can be added to the system software to gain more system functionality and/or reliability. The premise of this project was that bottlenecks in the software's interaction with the hardware platform could be found and explained to the end customer, identifying potential areas for software optimisation.

Figure 1: Observation of CPU idle and processing times.

Previous attempts to analyse performance in the lab were not successful, due to a lack of visibility into the hardware. The challenge was that the real time nature of the application required detailed visibility of the hardware activity as the software was executing. It was not possible to stop and continue the application and get meaningful results. It was also difficult to track the details of hardware components in the physical system, such as the state and activity of the cache or the stalling effect on the processor when accessing slow peripherals. The inherent difficulty of analysing the physical system was a major factor driving the need for a virtual prototype.

Modelling, simulation
After reviewing the available industry technological responses to this problem, our customer determined that creating an architecturally accurate performance model would be an effective approach to give the visibility required to understand the efficiency with which the software was using the hardware. The goal for this architectural model was to identify ways of optimising the software to make more efficient use of the hardware.

A TLM simulation environment adds internal hardware visibility to significantly improve the understanding of system activity and performance factors. Additionally, the simulation system can be fully analysed without any side effects that occur when attempting to analyse the real hardware. Our customer developed a successful strategy as follows:
1. Create and test models of the interesting portion of the platform: the HW/SW (CPU) interaction
2. Retarget an in-house Windows resident testbench application used in the lab for production test
3. Leverage standardised benchmarks to ensure simulated latencies match real hardware
4. Instrument the simulation environment to analyse system performance

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