Stay in touch with EE Times India

EE Times-India > Amplifiers/Converters

Amplifiers/Converters

# Boost DAC integral non-linearity through gain correction

Posted: 25 Oct 2011     Print Version

Keywords:digital-to-analogue converter  offset  gain error  non-linearity

The static absolute accuracy of a digital-to-analogue converter (DAC) can be described in terms of three fundamental kinds of errors: offset, gain error, and non-linearity. Of these three, linearity errors are the most difficult to handle since, in many applications, the user can null out the offset and gain errors, or compensate for them by building end-point auto calibration into the system design. Linearity errors, however, require more complex correction.

A DAC (figure 1) converts digital input codes to proportional analogue output signals, which could be either current or voltage. The resolution of a DAC refers to the number of unique output levels that the DAC is capable of producing. For example, a DAC with a resolution of 8bits will be capable of producing 28 (256) different output levels at its output. Ideally, each digital code provides equal analogue steps; however, in reality it cannot because of non-idealities.

 Figure 1: 8bit DAC symbol and role.

DAC linearity
Before looking at how to improve the integral non-linearity (INL) of a DAC, it would be best to review how we determine its linearity, as shown in figure 2. In a DAC, we focus primarily on two measures of its linearity: differential non-linearity (DNL) and integral non-linearity (INL).

DNL is the maximum deviation of an actual analogue output step between adjacent input codes, from the ideal step value (Δ). INL is the maximum deviation, at any point in the transfer function, of the actual output level from its ideal value. The ideal value is a straight line drawn between the actual zero and full-scale of the DAC.

 Figure 2: DAC linearity errors, DNL and INL.

The conventional end-point calibration technique is used to remove gain error in DACs. However, the gain error is typically not linear throughout the full-scale range of the DAC, because of various systematic non-idealities in silicon. These systematic patterns may cause unidirectional gradients that result in poor INL performance.

The major non-idealities that cause systematic patterns are as follows:
� Edge Effects, e.g. Length of Diffusion (LOD)
� Oxide thickness gradients resulting in a threshold shift across die
� Voltage drops in the supply lines

Therefore, an end-point calibration technique is not enough to remove gain error completely and can result in poor INL performance. Applications that require absolute output accuracy may require a much lower INL.

 Figure 3: Current-output DAC (IDAC) with ADC feedback.

1 • 2

Comment on "Boost DAC integral non-linearity thr..."
Comments: *  You can enter [0] more charecters.

Webinars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Search EE Times India
Services

﻿