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Why use SONOS memory for eflash

Posted: 13 Oct 2011     Print Version  Bookmark and Share

Keywords:embedded  non-volatile memory  Embedded flash  Silicon-Oxide-Nitride-Oxide-Silicon  SONOS 

The optimised thermal budget of SONOS integration ensures a negligible impact on the electrical parameters of existing CMOS devices. This means that with minimal changes, all the design IP of the original CMOS platform can be used in the embedded ICs. The SONOS process has shown no impact to 65-nm baseline design IP as well as device matching in high-volume production. Further, it has been shown that there is no impact to the baseline yield due to the integration of SONOS.

The table shows MOSFET parameter matching between embedded SONOS and pure CMOS baseline processes on key device parameters (P1= Priority 1 parameters; P2= Priority 2 parameters).

Table: MOSFET parameter matching between embedded SONOS and pure CMOS baseline processes on key device parameters.

The yield wafer maps on a SRAM product with the key SONOS process incorporated is compared with the baseline yield in the figure 5. It shows negligible impact of the SONOS process on the baseline yield.

Figure 4: SONOS Split #1 (left); SONOS Split #2 (center); Baseline CMOS (right).

The SONOS cell used in this macro can be adopted for an EEPROM also with minor changes in program/erase conditions. This enables easy integration of flash and EEPROM arrays on the same die.

Summary
SONOS technology is a low cost, highly reliable approach to embed nonvolatile memory into logic platforms. The CMOS design IP is virtually unchanged by SONOS integration. This technology has excellent endurance and data retention and is scalable to more advanced technology nodes with very little change in process integration. Cypress has successfully integrated its proprietary SONOS into the CMOS baseline at UMC and demonstrated a functional flash macro.

About the authors
Krishnaswamy Ramkumar has been involved in research and development of advanced semiconductor technologies at Cypress Semiconductor since 1993. He has contributed in technology nodes ranging from 0.50µm to 65 nm during this period. His work has been mainly in the front end processes such as Shallow trench Isolation, gate oxidation and ONO formation. He has 55 issued US patents to his credit. Ramkumar received his MS and PhD degrees from Indian Institute of Science, Bangalore. Prior to joining Cypress he was a faculty member at Indian Institute of Science and a Visiting Research Associate at Rensselaer Polytechnic Institute, Troy, NY.

Bo Jin directs Cypress's IP business unit as general manager, as well as develops strategic business relationships in Asia Operations. Prior to his current position, Bo Jin served as Director of Foundry of Cypress's Corporate Operation.

Bo built his career in many aspects, including roles as product manager, design program manager, and multi-multiple positions in technology R&D during his early years in Cypress. Bo started his job as night shift fab manufacturing sustaining engineer. Bo Jin received his B.S. degree in Material Science and B.A. degree in Economics & Business Management from Shanghai Jiao Tong University in 1992. He got his MS in material science from Arizona State University. He completed the Harvard Business School Executive MBA Program in 2007. He has 15 US patents.

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