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Employ CDCE62005 as clock synthesiser, jitter cleaner

Posted: 14 Oct 2011     Print Version  Bookmark and Share

Keywords:clock synthesiser  jitter cleaner 

Here's a guideline for using Texas Instruments CDCE62005 as a clock synthesiser or jitter cleaner to meet the requirements of different applications. Choosing the PLL loop bandwidth is critical for both clock generation (synthesising) and jitter cleaning modes. Depending on the input clock phase noise, the PLL loop bandwidth can be optimised to ensure the best possible phase noise performance at the clock outputs.

View the PDF document for more information.

Originally published by Texas Instruments at as "Phase Noise Performance and Loop Bandwidth Optimization of CDCE62005".

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