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Efficiently measure DDR3 signal integrity

Posted: 26 Jul 2011     Print Version  Bookmark and Share

Keywords:DDR3  signal integrity  time domain reflectometry 

It can be observed in the table that ODT increase leads to increase in gain adjustment, which needs to be performed. This is because ODT resistor values start nearing the probe impedance value.

Finally, there is a set of de-skewing numbers that the module manufacturer provides for each DDR signal. In case these numbers are not available, they can be obtained by performing time domain reflectometry (TDR) measurements on various signal bits. These numbers are used to compensate for signal length routing mismatches on the DIMM. These numbers are needed to be programmed in the oscilloscope channel settings[4].

We used the above setup to perform Signal Integrity measurements on a CMOS 45nm SOC having DDR3 Memory interface. As shown in figure 8 and figure 9 clean waveforms were observed.

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Figure 8: Address bits (green and purple) with respect to clock signal (Yellow) captured in oscilloscope persistence mode. Monotonic nature of the signal edges can be observed.

Measurements were repeatable over time. We observed clean edges in the DC regions of the waveform, confirming reduced noise in the measurements. Quality of the signal waveform was good as can be seen in the captures (compare with figure 2). All edges were observed to be monotonic. Unlike active probe setups, this setup proved to be robust for the entire measurement period, which spanned many months.

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Figure 9: Data bit eye (green) with respect to differential DQS (orange) signal captured in oscilloscope persistence mode with different data patterns. Signals display clean monotonic edges without any kinks. Observe DQS (Orange) wave shapes are a clear trapezoid with sharp edges which qualifies the high bandwidth of the measurements.

On the basis of above experience, we would like to highlight the following limitations/scope for improvement.

i. In future designs of the DIMM, skew between signals should be minimised as it degrades measurement accuracy.

ii. Clk & Clk_B signals on the DIMM module had large skew between them, which degraded clock crossover measurements. Future DIMM designs should address this point.

iii. Probe series load resistance values should be chosen considering the noise floor of the Oscilloscope and the signal loading effects.

iv. Transaction level debugging, which requires a large number of address, control signals to be captured, will be difficult to do on this platform. In future, we plan to design fixtures to connect these signals to LA as well.

The technique, discussed here, is able to reduce the signal integrity capture and measurement time by a factor of 10x as compared to the active probing methods. The quality of the results shows that this method can be used to probe a variety of high pin count interfaces like DDR, XDR etc. The results obtained from these measurements were successfully used by us in the Lab for all characterisation purposes.



3. Johnson Howard, Graham Martin, 'High Speed Digital Design: A Handbook of Black Magic', Prentice Hall PTR, 1993.

4. Agilent Technologies,'Probe De-Skew and Calibration'



- Atul Gupta, Rajeev Sharma and Manas Chhabra
  Freescale Semiconductors

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