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Simulator supports Xilinx FPGA hardware verification

Posted: 08 Jun 2011     Print Version  Bookmark and Share

Keywords:engineers  verification tool  simulators 

MathWorks launches EDA Simulator Link 3.3 with new FPGA-in-the-loop (FIL) capabilities for Xilinx FPGA development boards to enable design verifications at hardware speeds while using Simulink as a system-level test bench.

The introduction of FIL is said to add to the comprehensive set of HDL verification options that EDA Simulator Link supports for algorithms created in MATLAB and Simulink. FPGA-based verification provides higher run-time performance than is possible with HDL simulators and increases confidence that the algorithm will work in the real world.

The simulator verifies HDL implementations of MATLAB code and Simulink models using FPGA development boards for both Spartan and Virtex class devices, including the Virtex-6 ML605 development board.

The tool also uses co-simulation with Mentor Graphics ModelSim, Mentor Graphics Questa, and Cadence Design Systems Incisive Enterprise Simulator. It generates TLM 2.0 components for SystemC virtual prototyping environments.

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