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DDR3 design requirements for KeyStone devices

Posted: 08 Jun 2011     Print Version  Bookmark and Share

Keywords:DDR3 interface  DSP  DRAM 

This document provides implementation instructions for the DDR3 interface incorporated in the Texas Instruments Keystone series of DSP devices. It supports 1333 MT/s and higher memory speeds in a variety of topologies (see to the Data Manual for supported speeds). This document assumes the user has a familiarisation with DRAM implementation concepts and constraints. When searching for a particular configuration see the appendix, which will alleviate the need for searching the entire document which contains all possible variations.

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