Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Embedded

Learn about test tools for PCIe 3.0 designs

Posted: 31 May 2011     Print Version  Bookmark and Share

Keywords:PCIe  hardware  software  design 

It took five years for the industry to migrate from PCI Express 1.0 (introduced in 2002) to PCI Express 2.0 (introduced in 2007). Now, the next wave is here—PCI Express 3.0.

Known commonly as PCIe Gen 1, Gen 2 or Gen 3, reflecting on successive generations, it's the preferred interconnect for scalable systems, devices and applications such as high-end graphics, fault-tolerant clusters, and storage IO sharing networks. PCIe Gen 3 features 8Gb/s bandwidth, which is double that of Gen 2, while preserving compatibility with software and mechanical interfaces. It also has better provisions for reduced power, signal and data integrity, new transmit and receive equalisation methods, and clock data recovery.

Anticipating this new wave of Gen 3 systems and devices, new test tools will be needed to ensure the hardware and software are functional and work together. This article will survey those hardware and software tools for validation, compliance and general testing.

View the PDF document for more information.

Comment on "Learn about test tools for PCIe 3.0 ..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top