Global Sources
EE Times-India
EE Times-India > EDA/IP

Cadence enhances Silicon Realisation with Altos buy

Posted: 12 May 2011     Print Version  Bookmark and Share

Keywords:Silicon Realisation  foundation IP  SoC implementation 

Cadence Design Systems Inc. buys Altos Design Automation Inc., a provider of tools that enable fast, accurate characterisation of memory, standard cell libraries and other foundation IP, generating required models for SoC implementation. Financial terms of the deal were not disclosed.

Cadence says that when combined with Cadence's end-to-end Silicon Realisation portfolio, the offering gives its customers greater visibility into the effects of noise, timing, and power at every phase of the design cycle, including foundation IP design creation, extraction, SPICE simulation, and implementation.

Altos was founded in January 2005 by former employees of Cadence and CadMOS Design Technology, a physical layout and signal integrity software start-up that was acquired by Cadence in 2001. Altos founders include Jim McCanny, Altos CEO and former timing and signal integrity marketing group director at Cadence; Ken Tseng, Altos chief technology officer and a former architect at Cadence; Kevin Chou, Altos vice president of R&D and former senior member of Cadence's consulting staff; and Wenkung Chu, Altos R&D architect and also a former senior member of Cadence's consulting staff.

A spokesperson for Cadence did not immediately respond to an inquiry about whether the founders and other employees of Altos would join Cadence as a result of the acquisition.

But a statement issued by Cadence quotes McCanny saying he was "looking forward to working with Cadence to further exploit the capabilities of our characterisation technology, and help deliver a more powerful combined solution that overcomes our customers' most difficult design challenges."

"Foundation IP characterisation is becoming mission critical at advanced nodes due to shrinking time-to-market windows, escalating low-power, high-speed design complexities, and variations in advanced processes," says Chi-Ping Hsu, senior R&D vice president in Cadence's Silicon Realisation Group. "By extending our Silicon Realisation tool offering to include technically superior solutions that automate vital phases of the design process, we deliver the end-to-end approach that is required to ensure our customers' success."

Altos has more than 30 customers, including 11 of the top 20 semiconductor companies, according to the statement issued by Cadence.

- Dylan McGrath
  EE Times

Comment on "Cadence enhances Silicon Realisation..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top