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Optoelectronics/Displays  

Serdes IP powers next-gen flat panel displays

Posted: 22 Mar 2011     Print Version  Bookmark and Share

Keywords:Serdes IP  V-by-One standard  iDP technology  LVDS 

The company hopes to generate a buzz in the Serdes market, where it bills itself as the "integrated clocking and interconnect IP partner." Last month, it announced the commercial availability of the industry's lowest-power, 40nm Serdes IP. The breakthrough is said to be a programmable macro that supports multiple protocols, including PCI Express, SATA, XAUI, XFI and SGMII.

Now, Analog Bits wants to bring its Serdes IP into the next-generation display front, but there are some challenges. Today, the display vendors are making use of LVDS parts at the 130nm node. Because they are reluctant to make a quantum leap to the 40nm node, Analog Bits is offering IP that is "ported back to 65- and 90nm," Tirupattur said.

Analog Bits also faces competition from stand-alone Serdes vendors, such as Broadcom, Marvell and Synopsys. AMD, Intel, Nvidia and others devise Serdes technology for their own processor products.

Thine Electronics also offers a Serdes line, but the Japanese company is also driving a video standard in V-by-One HS. V-by-One HS is an advanced high-speed interface standard that is gaining steam. It can reduce the number of cables between DTV panels and DTV controllers as well as related connectors.

It offers capabilities for DTV markets that are requiring ever-higher frame rates and higher resolutions such as ultra-high-definition (UD) display panels with 4K x 2K (3,840 x 2,160) pixels. Thine's variable speed technology from 600Mbit/s to 3.75Gbit/s effectively meets the requirements of various different pixel rates and even 21:9 HDTV and cinema resolution televisions.

Analog Bits supports V-by-One and iDP. To help customers, the IP house offers a transmitter, receiver or combo IP. For example, in a transmitter configuration, the IP is said to have a total silicon area of 0.44sq. mm, a die size of 1.365mm and a power of 135mW. This is a savings of 15mm of area and over a half of a Watt, as compared to a LVDS 8 link device, according to the firm.

In a receiver configuration, the IP is said to have a total silicon area of 0.64sq. mm, a die size of 1.68mm and a power of 150mW. This is a savings of 9mm of area and over a half of a Watt, according to the firm. Analog Bits is also offering combo transmitter IP, which supports V-by-One and iDP.

- Mark LaPedus
  EE Times


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