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Parallel algorithm boosts cell phone video quality

Posted: 28 Feb 2011     Print Version  Bookmark and Share

Keywords:HEVC standard  CABAC  parallel-programming algorithm 

A paper presentation by a Texas Instrument researcher at the International Solid State Circuits Conference describes a parallel algorithm that could be incorporated into the High Efficiency Video Coding (HEVC) standard, the follow-on to the currently used H.264/AVC standard to offer considerably improved quality and power consumption of future systems, specifically those that generate or play video on devices ranging from 3D TV to cell phones.

The parallel method claims the ability to handle both existing and forthcoming compression standards.

The HEVC project aims to deliver by January 2013 a successor to today's mainstream H.264/AVC standard. It targets a 50 per cent improvement in coding efficiency, enabling Quad Full HD video resolutions of up to 4,096 x 2,160pixels.

"There are test models people are building on and modifying now," Vivienne Sze, a member of technical staff at TI told EE Times, suggesting the standard already is more than half done.

As many as 250 people have been attending the quarterly HEVC meetings, making hundreds of contributions so far. Sze presented her work on one of those HEVC contributions, a parallel-programming algorithm created as part of a doctoral thesis at MIT.

Sze defined a new and highly parallel version of the existing Context-based Adaptive Binary Arithmetic Coding (CABAC) scheme used in today's H.264/AVC codecs. She called CABAC "a well-known bottleneck [due to its] tight feedback loops."

The new technique creates a CABAC data structure which breaks up a video frame into several parts called interleaved entropy slices that can be processed in parallel. It further breaks those slices into several elements such as motion vectors and coefficients which also can be processed in parallel.

The ISSCC paper mapped the parallel CABAC algorithm onto a novel chip with 16 separate slice processors and 80 arithmetic decoders working in parallel. The technique could be used on any multi-core architecture, Sze said.

The paper claimed the algorithm and chip could deliver six- to ten-fold increases in performance over published CABAC architectures. Specifically, the test chip decoded a 300Mbit/s H.264/AVC stream at 1V, achieving a 2.3Gbit/s bit rate. That's fast enough to support the Quad Full HD resolution at 186fps or at 24fps when generating 7.8 views using Multiview Video Coding for stereoscopic 3D video.

The massively parallel CABAC algorithm has been adopted into the so-called JM-KTA working code of the HEVC group. A decision whether to make it a part of the standard is still pending.

- Rick Merritt
  EE Times

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