Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > Processors/DSPs
 
 
Processors/DSPs  

I/O register access latency

Posted: 03 Mar 2011     Print Version  Bookmark and Share

Keywords:RX600  latency  main bus 

This document by Renesas Electronics Corp. provides reference information to help determine the number of cycles (latency) the RX600 Series CPU takes to access an I/O register. It summarises some key points to consider in identifying that latency.

The number of cycles (latency) from the time the RX600 Series CPU executes an I/O register access instruction to the time a value is stored in the I/O register depends on:
- Number of bus cycles on internal main bus 1
- Number of cycles for divided-frequency clock synchronisation
- Number of bus cycles on the internal peripheral bus

This application note describes bus operation which takes place when the RX600 Series CPU accesses an I/O register. It also describes the operation from the standpoint of an I/O register. Thus, this is different from the CPU pipeline operation.

View the PDF document for more information.





Comment on "I/O register access latency"
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top