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Bus master DMA performance demo ref design for Xilinx PCIe

Posted: 18 Feb 2011     Print Version  Bookmark and Share

Keywords:Direct Memory Access  Virtex-6  Spartan-6 

This application note discusses how to design and implement a bus master direct memory access (DMA) design using Xilinx PCI Express Endpoint solutions. A performance demonstration reference design using Bus Master DMA is included with this application note. The reference design can be used to gauge achievable performance in various systems and act as a starting point for an application-specific Bus Master DMA. The reference design includes all files necessary to target the Integrated Blocks for PCI Express on Virtex-6 and Spartan-6, the Endpoint Block Plus Wrapper Core for PCI Express using the Virtex-5 Integrated Block for PCI Express, and the Endpoint PIPE for PCI Express targeting the Xilinx Spartan-3 family of devices. Also provided with the BMD hardware design is a DMA kernel mode driver for both Windows and Linux along with both a Windows 32-bit and Linux software application. Source code is included for both Linux and Window drivers and application.

View the PDF document for more information.

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