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Timer A operation using two-phase pulse signal and quadrupled processing

Posted: 17 Feb 2011     Print Version  Bookmark and Share

Keywords:R32C/100  quadrupled processing 

This document by Renesas Electronics Corp. describes timer A operation using a two-phase pulse signal and quadrupled processing in event counter mode with the R32C/100 Series.

When using the event counter mode of timer A4, the timer counts a two-phase pulse signal applied to pins TA4IN and TA4OUT using quadrupled processing. When an overflow or underflow occurs, a high is output from the corresponding port.

View the PDF document for more information.





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