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Logic analyser offers digital info capture functions

Posted: 08 Feb 2011     Print Version  Bookmark and Share

Keywords:logic analyser  narrow pulse interference  debugging  verification 

GAO Tek Inc. presents a logic analyser that is designed to sample up to 34 input channels while simultaneously being able to observe a sizeable amount of data and data flow direction control information.

This logic analyser enables a variety of digital information capture functions, as well as a large memory capacity, triggers and triggered procedures. The device is designed for capturing narrow pulse interference and the response of digital systems for debugging and verification.

In particular, logic analyser model 5034 not only identifies error messages while locating faults in the source code but also returns dynamic analysis results in binary, decimal, hexadecimal or ASCII format to aid debugging. Inputs include TTL, LVTTL, CMOS, LVCOMS, ECL, PECL and EIA. The device requires a minimum time resolution of 2ns, an input voltage range of -60V to 60V and a logic threshold range from -6V to 6V. A software CD with demo code in VC, CVI, VB, and LABVIEW is provided with the device, which runs under Windows 2000 to Windows Vista.

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