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GlobalFoundries readies 28nm digital design flow

Posted: 18 Jan 2011     Print Version  Bookmark and Share

Keywords:28nm  Super Low Power technology  Gate First High-k Metal Gate 

GlobalFoundries rolls out the 28nm silicon-validated signoff-ready digital design flows offering chip designer with the next generation of power-sensitive mobile and consumer electronic devices.

Developed in collaboration with EDA/IP ecosystem leaders and based on its 28nm Super Low Power (SLP) technology with Gate First High-k Metal Gate (HKMG), the flows are precisely tuned to help overcome the unique challenges of designing and manufacturing integrated circuits at leading edge nodes.

The signoff-ready flows were developed with recognition of the need for silicon validation to ensure first-time-right silicon success, setting a new standard for quality, scope, and relevance in foundry flows. Customers can now produce signoff ready 28nm designs using the industry's most advanced set of synthesis, place and route, sign-off, and DFM tools, tool scripts, and methodologies.

In addition to tight integration with GlobalFoundries ' signoff physical verification solution, all flows leverage the company's Design-for-Manufacturing (DFM) which supports DRC+, the company's silicon-validated solution that uses two-dimensional shape-based pattern-matching apart from standard Design Rule Checking (DRC) claiming up to a 100-fold speed improvement in identifying complex manufacturing issues without sacrificing accuracy.

A prerequisite in developing advanced flows is rigorous qualification of the digital routers. Accordingly, GlobalFoundries has developed a stringent set of requirements that digital routers from Cadence, Synopsys, Mentor Graphics, and Magma must fulfil in order to be qualified as signoff-ready. These consist of satisfying physical verification signoff rules and recommended rules, run time and memory footprints, as well as quality of results. The signoff-ready flows and router qualifications are supported by a full suite of 28nm-SLP Artisan advanced physical IP from ARM, including standard cells, power management kit, memory compilers, and interface IP.

Finally, all of GlobalFoundries ' 28nm technologies employ the Gate First approach to HKMG, which shares the process flow, design flexibility, design elements and benefits of all previous nodes based upon Poly SiON gates.

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