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Speculations cast on semiconductor technology roadmaps

Posted: 15 Dec 2010     Print Version  Bookmark and Share

Keywords:International Electron Device Meeting  transistor  process 

The 2010 International Electron Device Meeting (IEDM) was marked by a decline in the number of relevant papers presented this year compared to previous years, as chipmakers showed reluctance to reveal their latest plans on semiconductor technology roadmaps.

There was also a lack of consensus about the transistor structure for future nodes, and despite emerging technologies, chipmakers say that economics and cost will drive their future transistor and process decisions.

The chase after Moore�s Law drove chipmakers in the past to keep developing leading-edge processes as quickly as they could, which led to a plethora of relevant papers at IEDM. Today, however, there are fewer leading-edge chipmakers, contributing to a ''big drop" in papers at this year�s event, said Meikei Ieong of Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) and general chairman at IEDM. ''I don�t see (the amount of IEDM papers from the peak years) coming back," he said during an event.

There are other reasons for a decline in papers. In the past IEDM events, leading-edge chipmakers were more open and would often provide a hint on what�s coming on the horizon. IBM, Intel, Samsung, Toshiba, TSMC, UMC and others would reveal their latest and greatest processes amid an avalanche of papers.

At this years� event though, few papers that provided clues on vendors' plans. Chipmakers kept their cards close to the vest and didn�t want to reveal their directions to their rivals. Many papers were academic in nature or were short on detail.

In place of clear presentations on plans for 22-/20nm plans, rumours abounded, with many believing the leading-edge foundries will extend bulk CMOS.

One big source of speculation is what Intel Corp. will do at that node. Some say Intel will extend bulk CMOS. Others think the chip giant could go to fully-depleted-or sometimes called extra thin silicon-on-insulator (SOI). One source even thinks Intel is looking at tri-gate structures at 22- or at 15nm.

The wild card among the technology candidates is 3D based on through-silicon vias (TSVs), which is not process dependent. If chipmakers can produce TSV-based 3D chips in volumes-and at reasonable costs, it could throw a wrench in the entire roadmap.

Right now, leading-edge chipmakers are using conventional bulk CMOS and planar transistor structures for the 32-/28nm nodes. But clearly, there is still ''angst over the 20nm node and what transistor would be picked," said G. Dan Hutcheson, CEO, VLSI Research Inc. ''As for transistor structure, the safe bet is that we will extend conventional CMOS another generation."

Joanne Itow, an analyst with Semico Research Corp., agreed-and for good reason: Cost. It is simply too expensive and risky to move new and exotic transistor structure at 22-/20nm, Itow said.


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