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Industry challenges in IC scaling

Posted: 13 Dec 2010     Print Version  Bookmark and Share

Keywords:IC  chip scaling  3D  through-silicon via 

The cost and expense of chip scaling as IC technology enters sub-20nm era will drive the industry to think about new materials, structures and processes, according to a technologist from Samsung Electronics Co. Ltd.

During a keynote at the 2010 International Electron Device Meeting (IEDM), Kinam Kim, president of Samsung Advanced Institute of Technology, said that the cost of IC scaling could force the industry to migrate to 3-D devices, based on through-silicon via (TSV) technology.

He said that memory technology will scale to the 1xnm node, but the industry must also look at a new class of products that could replace existing DRAM and NAND, such as magnetoresistive RAM (MRAM), phase-change and Resistive ram (ReRAM).

"The current 30nm node silicon technology is meeting the demand for extremely low power, multi-functional chips that are able to maintain high performance to process and store huge amounts of heterogeneous data," Kim noted. "However, there are concerns on whether the current silicon technology can satisfy the technical requirements and overcome the ultimate limits attached to transistors scale down."

Here are some of Kim's predictions and the associated challenges presented during the keynote:

1. Logic scaling

"At gate lengths less than 20nm, the use of conventional planar transistors will be nearly impossible because of the extremely thin gate dielectric and junction depths," Kim said.

"Fortunately, silicon technology can be extended thanks to fully depleted (FD) devices such as FD-SOI and multi-gate (MuG) FinFETs. FD device technology is being transferred from R&D to manufacturing. It is expected that the EOT of MuG devices would follow the same trend as the historical SiON EOT trend."

2. TSV-based 3D parts

Scaling is becoming expensive, causing chipmakers to look at TSV-based devices. "Many groups have reported through-silicon-via based 3D IC (TSV-3D IC) where a single integrated circuit is built by stacking silicon wafers or dies and interconnecting them vertically so that they behave as a single device," Kim said.

"There are many challenging processes such as TSV sidewall etch profiles, poor isolation liners and barrier profiles. These can cause TSV reliability issues due to copper diffusion into the bulk material. In addition to process challenges, there are chip design related issues that need to be resolved in order to maximise the advantage of the TSV-3D IC technology. These issues are: 3D floor-planning (TSV size, the proximity of TSVs to neighbouring transistors, and routing with TSVs), thermal management, coefficient of thermal expansion (CTE) mismatch between Cu and Si and mechanical stability," he added.

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