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SMIC adopts Cadence tools for 65nm design

Posted: 09 Dec 2010     Print Version  Bookmark and Share

Keywords:nSilicon Realisation Technology  design-for-manufacturing  low-power technology 

Semiconductor Manufacturing International Corp. (SMIC) and Cadence Design Systems Inc. have collaborated to produce an integrated end-to-end Silicon Realisation flow for 65nm system-on-chip (SoC) designs. They said Cadence's Encounter Digital Implementation System was used as the foundation for the design-for-manufacturing (DFM) and low-power technology at the centre of SMIC's 65nm Reference Flow 4.1.

After thorough evaluation, SMIC chose the Cadence Silicon Realisation products based on their reliable hierarchical flow for large-scale designs and superior quality of results. SMIC emphasized that the tight flow integration across functional, physical, and electrical domains—for estimation, logic design, verification, physical implementation and in-design signoff technologies—offered a significant increase in both designer productivity as well as ease of use, and gave an output with more deterministic results.

The Cadence Silicon Realisation technology applied in the SMIC flow consists of Incisive Enterprise Simulator, Encounter RTL Compiler, Encounter Test, Encounter Conformal Low Power, Encounter Conformal Equivalence Checker, Encounter Digital Implementation System, QRC Extraction, Encounter Timing System, Encounter Power System, Litho Physical Analyser, Litho Electrical Analyser, Cadence CMP Predictor and Assura Physical Verification.

Senior director of design service at SMIC, Min Zhu states, "Our mutual customers can greatly benefit from the Cadence contributions to Reference Flow 4.1, which address two important challenges they face at 65nm�design margins and yields." He explains, "Deploying the full end-to-end Cadence Silicon Realisation flow for digital design, verification, and implementation along with our reference flow will enable our customers to work more efficiently and productively towards improving silicon quality and shrinking time to market."

Recently, Cadence also launched a new holistic approach to Silicon Realisation which upgrades chip development beyond its traditional patchwork of point tools to a streamlined end-to-end path of integrated technology, tools, and methodology. This novel approach is targeted on realising products and technologies which deliver on the three demand of a deterministic path to silicon, namely: unified design intent, abstraction, and convergence. As a key element of the Cadence EDA360 strategy, this approach aims to ramp up productivity, predictability and profitability, at the same time minimising the risk.

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