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Implement DDR2 SDRAM interface in FPGA

Posted: 10 Dec 2010     Print Version  Bookmark and Share

Keywords:Xilinx  Memory Interface Generator too  Virtex-5 

This application note by Xilinx describes a 667 Mb/s DDR2 SDRAM interface implemented in a Virtex-5 device. A customized version of this reference design can be generated using the Xilinx Memory Interface Generator tool.

DDR2 SDRAM uses a source synchronous interface for transmission and reception of data. On a read, the data and strobe are transmitted edge aligned by the memory. To capture this transmitted data using Virtex-5 FPGAs, either the strobe and/or data can be delayed. In this design, the read data is captured in the delayed strobe domain and recaptured in the FPGA clock domain using a combination of the Input Double Data Rate and Configurable Logic Block flip-flops.

View the PDF document for more information.

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