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Interfacing FPGA to JESD204A compliant ADC

Posted: 06 Dec 2010     Print Version  Bookmark and Share

Keywords:Virtex-5  JEDEC Standard No. 204A  two-lane dual ADC 

This application note describes how to interface the Virtex-5 LXT, SXT, TXT, and FXT devices featuring GTP/GTX transceivers to an analog-to-digital converter (ADC) compliant to JEDEC Standard No. 204A (JESD204A) Serial Interface for Data Converters. With some restrictions that are highlighted in the text, this application note can also be used for ADC devices compliant to the older JESD204 standard.

The JESD204A standard describes a serialized interface between data converters and logic devices. It contains normative information to enable the implementation of designs that communicate with devices covered by the JESD204A standard.

This application note discusses the implementation of a two-lane dual ADC with each lane having a 14-bit resolution and running at 125 MSPS. It provides an overview of how to implement the serial data interface and the link protocol described in the JESD204A standard. Although some implementation modes are discussed in this application note, not all possible implementation modes are provided in the accompanying reference design.

View the PDF document for more information.

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