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PLL through dynamic reconfiguration port

Posted: 07 Dec 2010     Print Version  Bookmark and Share

Keywords:Spartan-6  clock output frequency  dynamic reconfiguration port 

This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the Spartan-6 FPGA phase locked loop (PLL) through its dynamic reconfiguration port (DRP). An explanation of the behavior of the internal DRP control registers is accompanied by a reference design. The reference design uses a state machine to drive the DRP to ensure that the registers are controlled in the correct sequence.

Although the reference design performs the operations for the user, familiarity with the functional operation of the PLL is recommended. The PLL used in conjunction with the DRP interface is recommended for advanced users when the basic PLL functionality is not sufficient.

The DCM_CLKGEN primitive can be a useful alternative to using the PLL with the DRP interface. The reference design supports two reconfiguration state addresses and can be extended to support additional states. Each state does a full reconfiguration of the PLL so that most parameters can be changed.

View the PDF document for more information.

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