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SFI-4.1 SDR interface with bus alignment

Posted: 06 Dec 2010     Print Version  Bookmark and Share

Keywords:SFI-4.1  deserialization  forwarded clock 

This application note describes an SFI-4.1 reference design that implements the OIF-SFI4-01.01 interface, a 16-channel, source-synchronous LVDS interface operating at single data rate (SDR). The transmitter requires 16 LVDS pairs for data and one LVDS pair for the forwarded clock. The transmitter operates at 4:1 serialization on each of the 16 data channels. The receiver also requires 16 LVDS pairs for data and one LVDS pair for the source-synchronous clock input. The receiver operates at 1:4 deserialization on each of the 16 data channels. The timing of the receiver is described in depth and is characterized in hardware.

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